MPC8360CVVALDGA datasheet(21/102 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

DDR and DDR2 SDRAM AC Electrical Characteristics

This table provides the input AC timing specifications for the DDR SDRAM interface when GVDD(typ) = 2.5 V.

This figure shows the input timing diagram for the DDR controller.

Figure 6. DDR Input Timing Diagram

Table 19. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions with GVDD of 2.5 V ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

VIL

—MVREF – 0.31

—

AC input high voltage

VIH

MVREF + 0.31

—

Table 20. DDR and DDR2 SDRAM Input AC Timing Specifications Mode

At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

MDQS—MDQ/MECC input skew per byte

333 MHz

266 MHz

200 MHz

tDISKEW

–750

–1125

–1250

750

1125

1250

1, 2

Notes:

1. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.

2. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0

≤n ≤7)

or ECC (MECC[{0...7}] if n = 8).

MCK[n]

tMCK

MDQ[x]

MDQS[n]

tDISKEW

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