ADL5565ACPZ-R7 datasheet(23/29 Pages) AD

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Data Sheet

ADL5565

Rev. D | Page 23 of 28

SOLDERING INFORMATION AND RECOMMENDED

PCB LAND PATTERN

Figure 44 show s the recommended land pattern for the ADL5565.

The ADL5565 is contained in a 3 × 3 mm LFCSP package, which

has an exposed ground paddle (EPAD). This paddle is internally

connected to the ground of the chip. To minimize thermal

impedance and ensure electrical performance, solder the paddle

to the low impedance ground plane on the PCB. To further

reduce thermal impedance, it is recommended that the ground

planes on all layers under the paddle be stitched together with vias.

For more information on land pattern design and layout, refer

to the AN-772 Application Note, A Design and Manufacturing

Guide for the Lead Frame Chip Scale Package (LFCSP).

This land pattern, on the ADL5565 evaluation board, provides

a measured thermal resistance (θJA) of 60°C/W. To measure θJA,

the temperature at the top of the LFCSP package is found with

an IR temperature gun. Thermal simulation suggests a junction

temperature 1.5°C higher than the top of package temperature.

With additional ambient temperature and I/O power measure-

ments, θJA could be determined.

36mils

19.7mils

10mils

59mils

Figure 44. Recommended Land Pattern

EVALUATION BOARD

Figure 45 shows the schematic of the ADL5565 evaluation board.

The board is powered by a single supply in the 3 V to 5 V range.

The power supply is decoupled by 10 µF and 0.1 µF capacitors.

Table 16 details the various configuration options of the evaluation

board. Figure 46 and Figure 47 show the component and circuit

side layouts of the evaluation board.

To realize the minimum gain (6 dB into a 200 Ω load), Input 1

(VIN1 and VIP1) must be used by installing 0 Ω resistors at R3

and R4, leaving R5 and R6 open. R1 and R2 must be 33.2 Ω for

a 50 Ω input impedance.

Likewise, driving Input 2 (VIN2 and VIP2) realizes the middle

gain (12 dB into a 200 Ω load) by installing 0 Ω at R5 and R6

and leaving R3 and R4 open. R1 and R2 must be 50 Ω for a

50 Ω input impedance.

For the maximum gain (15.5 dB into a 200 Ω load), both inputs

are driven by installing 0 Ω resistors at R3, R4, R5, and R6. R1

and R2 are open for a 50 Ω input impedance.

The balanced input and output interfaces are converted to

single ended with a pair of baluns (M/A-COM ETC1-1-13).

The balun at the input, T1, provides a 50 Ω single-ended-to-

differential transformation. The output balun, T2, and the

matching components are configured to provide a 200 Ω to 50 Ω

impedance transformation with an insertion loss of about 11 dB.

As an alternative, the input transformer, T1, can be replaced with

one of the following transformers to provide a low loss balanced

input to the ADL5565.

•

6 dB gain configuration, Mini-Circuits TC4-1W+

•

12 dB gain configuration, Mini-Circuits, TC2-1T+

•

15.5 dB gain configuration, Mini-Circuits TC1.5-52T

When using these alternative transformers, R1 and R2 are left

open. Replace C1 and C2 with 0 Ω jumpers and add a 0.1 µF

capacitor to C12.

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