CC1150-RTR1 datasheet(40/67 Pages) TI

40 / 67 page

CC1150

SWRS037A

Page 40 of 60

responsibility to ensure that the system

complies with regulations.

24.2

Frequency Hopping and Multi-Channel Systems

The 315 MHz, 433 MHz, 868 MHz or 915 MHz

bands are shared by many systems both in

industrial, office and home environments. It is

therefore recommended to use frequency

hopping spread spectrum (FHSS) or a multi-

channel protocol because the frequency

diversity makes the system more robust with

respect to interference from other systems

operating in the same frequency band. FHSS

also combats multipath fading.

CC1150 is highly suited for FHSS or multi-

channel systems due to its agile frequency

synthesizer

and

effective

communication

interface. Using the packet handling support

and data buffering is also beneficial in such

systems as these features will significantly

offload the host controller.

Charge pump current, VCO current and VCO

capacitance array calibration data is required

for

each

frequency

when

implementing

frequency hopping for

CC1150. There are 3

ways of obtaining the calibration data from the

chip:

1) Frequency hopping with calibration for each

hop. The PLL calibration time is approximately

720 µs. The blanking interval between each

frequency hop is then approximately 810 µs.

2) Fast frequency hopping without calibration

for each hop can be done by calibrating each

frequency at startup and saving the resulting

FSCAL3

, FSCAL2 and FSCAL1 register values

in MCU memory. The VCO capacitance

calibration FSCAL1 register value must be

found for each RF frequency to be used. The

VCO current calibration value and the charge

pump current calibration value available in

FSCAL2

and FSCAL3 respectively are not

dependent on the RF frequency, so the same

value can therefore be used for all RF

frequencies for these two registers. Between

each frequency hop, the calibration process

can then be replaced by writing the FSCAL3,

FSCAL2

and FSCAL1 register values that

corresponds to the next RF frequency. The

PLL turn on time is approximately 90 µs. The

blanking interval between each frequency hop

is then approximately 90 µs.

3) Run calibration on a single frequency at

startup. Next write 0 to FSCAL3[5:4] to

disable the charge pump calibration. After

writing to FSCAL3[5:4], strobe STX with

MCSM0.FS_AUTOCAL=1

for

each

new

frequency hop. That is, VCO current and VCO

capacitance calibration is done, but not charge

pump current calibration. When charge pump

current calibration is disabled the calibration

time is reduced from approximately 720 µs to

approximately 150 µs. The blanking interval

between

each

frequency

hop

then

approximately 240 µs.

There is a trade off between blanking time and

memory space needed for storing calibration

data in non-volatile memory. Solution 2) above

gives the shortest blanking interval, but

requires more memory space to store

calibration values. This solution also requires

that the supply voltage and temperature do not

vary much in order to have a robust solution.

Solution 3) gives approximately 570 µs smaller

blanking interval than solution 1).

The

recommended

settings

for

TEST0.VCO_SEL_CAL_EN

change

with

frequency. This means that one should always

use SmartRF Studio [11] to get the correct

settings for a specific frequency before doing a

calibration, regardless of which calibration

method is being used. It must be noted that

the content of the

CC1150 is not retained in

SLEEP state, and thus it is necessary to write

to the TEST0 register, along with other

registers, when returning from the SLEEP

state and initiating calibrations.

24.3

Wideband Modulation not using Spread Spectrum

Digital modulation systems under FFC part

15.247 include FSK and GFSK modulation. A

maximum peak output power of 1W (+30 dBm)

is allowed if the 6 dB bandwidth of the

modulated signal exceeds 500 kHz. In

addition, the peak power spectral density

conducted to the antenna shall not be greater

than +8 dBm in any 3 kHz band.

Operating at high data rates and frequency

deviation the

CC1150 is suited for systems

targeting compliance with digital modulation

system as defined by FFC part 15.247. An

external power amplifier is needed to increase

the output above +10 dBm. Please refer to

DN006 [5] for further details concerning

wideband modulation and

CC1150.

CC1150-RTR1 Datasheet(PDF) 40 Page - Texas Instruments

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