NQ80331M800 datasheet(13/67 Pages) INTEL

13 / 67 page

Specification Update

Intel® 80331 I/O Processor

Summary Table of Changes

Core Errata

No.

Steppings

Page

Status

Errata

A-1

B-0

C-0

D-0

D-1

XXX

No Fix

Abort is missed when lock command is outstanding

XXX

No Fix

Aborted Store that Hits the Data Cache May Mark Write-Back

Data as Dirty

XXX

No Fix

Performance Monitor Unit event 0x1 can be incremented

erroneously by unrelated events

XXX

No Fix

In Special Debug State, back-to-back memory operations —

where the first instruction aborts — may cause a hang

XXX

No Fix

Accesses to the CP15 ID register with opcode2 > 0b001

returns unpredictable values

XXX

No Fix

Disabling and re-enabling the MMU can hang the core or

cause it to execute the wrong code

XXX

No Fix

Updating the JTAG parallel registers requires an extra TCK

rising edge

XXX

No Fix

Non-branch instruction in vector table may execute twice after

a thumb mode exception

NQ80331M800 Datasheet(PDF) 13 Page - Intel Corporation

NQ80331M800 Datasheet(HTML) 13 Page - Intel Corporation

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