AD8250ARMZ-R7 datasheet(15/24 Pages) AD

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Data Sheet

AD8250

Rev. C | Page 15 of 24

THEORY OF OPERATION

10kΩ

REF

OUT

–IN

+IN

2.2kΩ

+VS

–VS

+VS

–VS

+VS

–VS

2.2kΩ

DGND

DIGITAL

GAIN

CONTROL

2.2kΩ

+VS

–VS

+VS

–VS

+VS

–VS

+VS

–VS

Figure 47. Simplified Schematic

The AD8250 is a monolithic instrumentation amplifier based

on the classic, 3-op-amp topology as shown in Figure 47. It is

fabricated on the Analog Devices, Inc., proprietary iCMOS®

process that provides precision, linear performance, and a

robust digital interface. A parallel interface allows users to

digitally program gains of 1, 2, 5, and 10. Gain control is achieved

by switching resistors in an internal, precision resistor array (as

shown in Figure 47). Although the AD8250 has a voltage feedback

topology, the gain bandwidth product increases for gains of 1, 2,

and 5 because each gain has its own frequency compensation.

This results in maximum bandwidth at higher gains.

All internal amplifiers employ distortion cancellation circuitry

and achieve high linearity and ultralow THD. Laser trimmed

resistors allow for a maximum gain error of less than 0.03%

for G = 1 and minimum CMRR of 98 dB for G = 10. A pinout

optimized for high CMRR over frequency enables the AD8250

to offer a guaranteed minimum CMRR over frequency of 80 dB

at 50 kHz (G = 1). The balanced input reduces the parasitics

that, in the past, adversely affected CMRR performance.

GAIN SELECTION

Logic low and logic high voltage limits are listed in the

Specifications section. Typically, logic low is 0 V and logic high

is 5 V; both voltages are measured with respect to DGND. See

Table 2 for the permissible voltage range of DGND. The gain of

the AD8250 can be set using two methods.

Transparent Gain Mode

The easiest way to set the gain is to program it directly via a

logic high or logic low voltage applied to A0 and A1. Figure 48

shows an example of this gain setting method, referred to through-

out the data sheet as transparent gain mode. Tie WR to the negative

supply to engage transparent gain mode. In this mode, any change

in voltage applied to A0 and A1 from logic low to logic high, or

vice versa, immediately results in a gain change. Table 5 is the

truth table for transparent gain mode, and Figure 48 shows the

AD8250 configured in transparent gain mode.

+15V

–15V

+IN

+5V

–IN

10μF0.1µF

G = 10

DGND

REF

AD8250

NOTE:

1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −VS.

THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE

THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE

SET TO LOGIC HIGH, RESULTING IN A GAIN OF 10.

Figure 48. Transparent Gain Mode, A0 and A1 = High, G = 10

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