REV. A

AD7470/AD7472

–6–

PIN FUNCTION DESCRIPTION

Pin

Mnemonic

Function

CS

Chip Select. Active low logic input used in conjunction with

RD to access the conversion result. The conversion

result is placed on the data bus following the falling edge of both

CS and RD. CS and RD are both connected to

the same AND gate on the input so the signals are interchangeable.

CS can be hardwired permanently low.

RD

Read Input. Logic Input used in conjunction with

CS to access the conversion result. The conversion result is

placed on the data bus following the falling edge of both

CS and RD. CS and RD are both connected to same

AND gate on the input so the signals are interchangeable.

CS and RD can be hardwired permanently low in which

case, the data bus is always active and the result of the new conversion is clocked out slightly before to the BUSY

line going low.

CONVST

Conversion Start Input. Logic Input used to initiate conversion. The input track/hold amplifier goes from track

mode to hold mode on the falling edge of

CONVST and the conversion process is initiated at this point. The con-

version input can be as narrow as 15 ns. If the

CONVST input is kept low for the duration of conversion and is

still low at the end of conversion, the part will automatically enter sleep mode. If the part enters this sleep mode,

the next rising edge of

CONVST wakes up the part. Wake-up time for the part is typically 1

µs.

CLK IN

Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the

AD7472 takes 14 clock cycles while conversion time for the AD7470 takes 12 clock cycles. The frequency of this

master clock input, therefore, determines the conversion time and achievable throughput rate. While the ADC is

not converting, the Clock-In pad is in three-state and thus no clock is going through the part.

BUSY

BUSY Output. Logic Output indicating the status of the conversion process. The BUSY signal goes high after the

falling edge of

CONVST and stays high for the duration of conversion. Once conversion is complete and the con-

version result is in the output register, the BUSY line returns low. The track/hold returns to track mode just prior

to the falling edge of BUSY and the acquisition time for the part begins when BUSY goes low. If the

CONVST

input is still low when BUSY goes low, the part automatically enters its sleep mode on the falling edge of BUSY.

REF IN

Reference Input. An external reference must be applied to this input. The voltage range for the external reference

is 2.5 V

±1% for specified performance.

Analog Supply Voltage, +2.7 V to +5.25 V. This is the only supply voltage for all analog circuitry on the AD7470/

apart even on a transient basis. This supply should be decoupled to AGND.

Digital Supply Voltage, +2.7 V to +5.25 V. This is the supply voltage for all digital circuitry on the AD7470/

must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND.

AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7470/AD7472. All analog input signals

and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages

should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis.

DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7470 and AD7472. The

DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart even

on a transient basis.

Analog Input. Single-ended analog input channel. The input range is 0 V to REFIN. The analog input presents a

high dc input impedance.

Supply Voltage for the Output Drivers, +2.7 V to +5.25 V. This voltage determines the output high voltage for the

ADC) while the digital outputs can interface to 3 V logic.

DB0–DB9/11

Data Bit 0 to Data Bit 9 (AD7470) and DB11 (AD7472). Parallel digital outputs that provide the conversion

result for the part. These are three-state outputs that are controlled by

CS and RD. The output high voltage level