WM8716

Production Data

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PD, Rev 4.2,August 2008

10

AUDIO DATA INTERFACE

Data may be input at a rate corresponding to the system clock having a rate of 256fs or 384fs or

512fs or 768fs, in which case an oversampling ratio of 128x is selected. Alternatively a rate of 128fs

or 192fs may be used, in which case the first filter stage is bypassed and an oversampling ratio of

64x results. Finally, in MODE8X, data may be input at 8x the normal rate, in which case separate

input pins are used to input the two stereo channels of data (unless DIFFHW mode and MODE8X

are both selected, in which case only a mono channel is converted differentially). In MODE8X all filter

stages are by-passed, prior to the sigma delta modulator. Data is input MSB first in all modes.

NORMAL SAMPLE RATE

In normal mode, the data is input serially on one pin for both left and right channels.

Data can be “right justified” meaning that the last 16, 20 or 24 bits (depending on chosen PCM word

length) that were clocked in prior to the transition on LRCIN are valid.

Alternatively data can be “left justified” (20 and 24-bit PCM data only), where the bits are clocked in

as the first 20 or 24 bits after a transition on LRCIN.

except with one additional preceding clock cycle.

LRCIN (PIN 1)

16-BIT RIGHT

JUSTIFIED

DIN (PIN 2)

20-BIT RIGHT

JUSTIFIED

DIN (PIN 2)

24-BIT RIGHT

JUSTIFIED

DIN (PIN 2)

24-BIT LEFT

JUSTIFIED

DIN (PIN 2)

20-BIT LEFT

JUSTIFIED

DIN (PIN 2)

BCKIN (PIN 3)

B2 B1 B0

B2 B1 B0

B2 B1

B0

B0

B0

B23 B22 B21

B19 B18 B17

B23 B22 B21 B20 B19

B4 B3 B2 B1 B0

B0

B19 B18 B17

B15

B2 B1 B0

B2 B1 B0

B2 B1 B0

B23 B22 B21

B19 B18 B17

B0

B4 B3 B2 B1 B0

B23 B22 B21 B20 B19

B19 B18 B17

B15

B2 B1 B0

B2 B1 B0

B2 B1 B0

RIGHT

LEFT

1/fs

LRCIN (PIN 1)

DIN (PIN 2)

DIN (PIN 2)

DIN (PIN 2)

BCKIN (PIN 3)

B2

B1 B0

B0

B2 B1 B0

B3 B2 B1

RIGHT

LEFT

B15

B23

B19

B6

B5 B4

B2

B1 B0

B3 B2 B1

B15

B23

B19

B6 B5 B4

B0

B2 B1 B0

B23

B19

B15

Figure 4 Audio Data Input Format