ADL5243ACPZ-R7 datasheet(21/32 Pages) AD

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Data Sheet

ADL5243

Rev. A | Page 21 of 32

Amplifier 1 Power Supply

AMP1 in the ADL5243 is a broadband gain block. The dc bias is

supplied through Inductor L1 and is connected to the

AMP1OUT pin. Three decoupling capacitors (C13, C14, and

C25) are used to prevent RF signals from propagating on the dc

lines. The dc supply ranges from 4.75 V to 5.25 V and should be

connected to the VCC test pin.

Amplifier 1 RF Input Interface

Pin 10 is the RF input for AMP1 of the ADL5243. The amplifier

is internally matched to 50 Ω at the input; therefore, no external

components are required. Only a dc blocking capacitor (C21) is

required.

Amplifier 1 RF Output Interface

Pin 6 is the RF output for AMP1 of the ADL5243. The amplifier

is internally matched to 50 Ω at the output as well; therefore, no

external components are required. Only a dc blocking capacitor

(C4) is required. The bias is provided through this pin via a

choke inductor, L1.

Amplifier 2 Power Supply

The collector bias for AMP2 is supplied through Inductor L2

and is connected to the AMP2OUT pin, whereas the base bias is

provided through Pin 16. The base bias is connected to the

same supply pin as the collector bias. Three decoupling

capacitors (C3, C20, and C25) are used to prevent RF signals

from propagating on the dc lines. The dc supply ranges from

4.75 V to 5.25 V and should be connected to the VCC2 test pin.

Amplifier 2 RF Input Interface

Pin 19 is the RF input for AMP2 of the ADL5243. The input of

the amplifier is easily matched to 50 Ω with a combination of

series and shunt capacitors and a microstrip line serving as an

inductor. Figure 56 shows the input matching components and

is configured for 2140 MHz.

Amplifier 2 RF Output Interface

Pin 15 is the RF input for AMP2 of the ADL5243. The output of

the amplifier is easily matched to 50 Ω with a combination of series

and shunt capacitors and a microstrip line serving as an inductor.

Additionally, bias is provided through this pin. Figure 56 shows

the output matching components and is configured for 2140 MHz.

DSA RF Input Interface

Pin 4 is the RF input for the DSA of the ADL5243. The input

impedance of the DSA is close to 50 Ω over the entire frequency

range; therefore, no external components are required. Only a

dc blocking capacitor (C1) is required.

DSA RF Output Interface

Pin 21 is the RF output for the DSA of the ADL5243. The

output impedance of the DSA is close to 50 Ω over the entire

frequency range; therefore, no external components are

required. Only a dc blocking capacitor (C5) is required.

DSA SPI Interface

The DSA of the ADL5243 can operate in either serial or parallel

mode. Pin 32 (SEL) controls the mode of operation. For serial

mode operation, connect SEL to ground, and for parallel mode

operation, connect SEL to VDD. In parallel mode, Pin 25 to Pin

30 (D6 to D1) are the data bits, with D6 being the LSB. Connect

Pin 31 (D0) to ground during parallel mode of operation. In

serial mode, Pin 29 is the latch enable (LE), Pin 30 is the data

(DATA), and Pin 31 is the clock (CLK). Pin 26, Pin 27, and Pin 28

are not used in the serial mode and should be connected to

ground. Pin 25 (D6) should be connected to VDD during the

serial mode of operation. To prevent noise from coupling onto

the digital signals, an RC filter can be used on each data line.

SPI TIMING

SPI Timing Sequence

Figure 58 shows the timing sequence for the SPI function using

a 6-bit operation. The clock can be as fast as 20 MHz. In serial

mode operation, Register B5 (MSB) is first, and Register B0

(LSB) is last.

Table 4. Mode Selection Table

Pin 32 (SEL)

Functionality

Connect to Ground

Serial mode

Connect to Supply

Parallel mode

Table 5. SPI Timing Specifications

Parameter

Limit

Unit

Test Conditions/Comments

FCLK

MHz

Data clock frequency

ns min

Clock high time

ns min

Clock low time

ns min

Data to clock setup time

ns min

Clock to data hold time

ns min

Clock low to LE setup time

ns min

LE pulse width

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