MPC8544E datasheet(20/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

DDR and DDR2 SDRAM

6.2.2

DDR SDRAM Output AC Timing Specifications

Table 18 provides the output AC timing specifications for the DDR SDRAM interface.

Table 18. DDR SDRAM Output AC Timing Specifications

At recommended operating conditions.

Parameter

Symbol1

Min

Max

Unit

Notes

MCK[n] cycle time, MCK[n]/MCK[n] crossing

tMCK

3.75

ADDR/CMD output setup with respect to MCK

tDDKHAS

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

—

ADDR/CMD output hold with respect to MCK

tDDKHAX

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

—

MCS[n] output setup with respect to MCK

tDDKHCS

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

—

MCS[n] output hold with respect to MCK

tDDKHCX

533 MHz

400 MHz

333 MHz

1.48

1.95

2.40

—

MCK to MDQS Skew

tDDKHMH

–0.6

0.6

MDQ/MECC/MDM output setup with respect

to MDQS

tDDKHDS,

tDDKLDS

533 MHz

400 MHz

333 MHz

538

700

900

—

MDQ/MECC/MDM output hold with respect to

MDQS

tDDKHDX,

tDDKLDX

533 MHz

400 MHz

333 MHz

538

700

900

—

MDQS preamble

tDDKHMP

0.75 x tMCK

—

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