AD8376ACPZ-R7 datasheet(12/24 Pages) AD

12 / 24 page

AD8376

Rev. A | Page 12 of 24

CIRCUIT DESCRIPTION

BASIC STRUCTURE

The AD8376 is a dual differential variable gain amplifier with

each amplifier consisting of a 150 Ω digitally controlled passive

attenuator followed by a highly linear transconductance

amplifier.

gm CORE

AMP

MUX BUFFERS

1/2 AD8376

A0 TO A4

DIGITAL

SELECT

ATTENUATOR

IP+

VCM

IP–

OP+

OP–

Figure 33. Simplified Schematic

Input System

The dc voltage level at the inputs of the AD8376 is set by an

internal voltage reference circuit to about 2 V. This reference is

accessible at VCMA and VCMB and can be used to source or

sink 100 μA. For cases where a common-mode signal is applied

to the inputs, such as in a single-ended application, an external

capacitor between VCMA/VCMB and ground is required. The

capacitor improves the linearity performance of the part in this

mode. This capacitor should be sized to provide a reactance of

10 Ω or less at the lowest frequency of operation. If the applied

common-mode signal is dc, its amplitude should be limited to

0.25 V from VCMA/VCMB (VCMA or VCMB ± 0.25 V). Each

device can be powered down by pulling the ENBA or ENBB pin

down to below 0.8 V. In the powered down mode, the total

current reduces to 3 mA (typical). The dc level at the inputs and

at VCMA/VCMB remains at about 2 V, regardless of the state of

the ENBA of ENBB pin.

Output Amplifier

The gain is based on a 150 Ω differential load and varies as RL is

changed per the following equations:

Voltage Gain = 20 × (log(RL/150) + 1)

and

Power Gain = 10 × (log(RL/150) + 2)

The dependency of the gain on the load is due to the open-

collector architecture of the output stage.

The dc current to the outputs of each amplifier is supplied

through two external chokes. The inductance of the chokes and

the resistance of the load determine the low frequency pole of

the amplifier. The parasitic capacitance of the chokes adds to

the output capacitance of the part. This total capacitance in

parallel with the load resistance sets the high frequency pole of

the device. Generally, the larger the inductance of the choke, the

higher its parasitic capacitance. Therefore, the value and type of

the choke should be chosen keeping this trade-off in mind.

For operation frequency of 15 MHz to 700 MHz driving a

150 Ω load, 1 μH chokes with SRF of 160 MHz or higher are

recommended (such as 0805LS-102XJBB from Coilcraft).

The supply current of each amplifier consists of about 50 mA

through the VCC pin and 80 mA through the two chokes

combined. The latter increases with temperature at about

2.5 mA per 10°C.

Each amplifier has two output pins for each polarity, and they

are oriented in an alternating fashion. When designing the

board, care should be taken to minimize the parasitic capaci-

tance due to the routing that connects the corresponding

outputs together. A good practice is to avoid any ground or

power plane under this routing region and under the chokes to

minimize the parasitic capacitance.

Gain Control

Two independent 5-bit binary codes change each attenuator

setting in 1 dB steps such that the gain of each amplifier

changes from +20 dB (Code 0) to −4 dB (Code 24 and higher).

The noise figure of each amplifier is about 8 dB at maximum

gain setting, and it increases as the gain is reduced. The increase

in noise figure is equal to the reduction in gain. The linearity of

the part measured at the output is first-order independent of

the gain setting. From 0 dB to 20 dB gain, OIP3 is approximately

50 dBm into 150 Ω load at 140 MHz (3 dBm per tone). At gain

settings below 0 dB, it drops to approximately 45 dBm.

AD8376ACPZ-R7 Datasheet(PDF) 12 Page - Analog Devices

AD8376ACPZ-R7 Datasheet(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL