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SC102205 Datasheet(PDF) 75 Page - Freescale Semiconductor, Inc |
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SC102205 Datasheet(HTML) 75 Page - Freescale Semiconductor, Inc |
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75 / 140 page ![]() Device User Guide — 9S12DT128DGV2/D V02.17 75 Freescale Semiconductor Section 3 System Clock Description 3.1 Overview The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation. Figure 3-1 Clock Connections CRG bus clock core clock EXTAL XTAL oscillator clock HCS12 CORE IIC RAM SCI0, SCI1 PWM ATD0, 1 BF Flash ECT BDLC SPI0, 1 CAN0, 1, 4 PIM EEPROM BDM MEBI INT CPU BKP MMC |
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