MPC8544VTALJ datasheet(35/120 Pages) FREESCALE

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MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.6.1

MII Transmit AC Timing Specifications

Table 32 provides the MII transmit AC timing specifications.

Figure 16 shows the MII transmit AC timing diagram.

Figure 16. MII Transmit AC Timing Diagram

8.6.2

MII Receive AC Timing Specifications

Table 33 provides the MII receive AC timing specifications.

Table 32. MII Transmit AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Notes

TX_CLK clock period 10 Mbps

tMTX

—400

—

TX_CLK clock period 100 Mbps

tMTX

—40

—

TX_CLK duty cycle

tMTXH/tMTX

—

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN

delay

tMTKHDX

—

TX_CLK data clock rise (20%–80%)

tMTXR

1.0

—

4.0

—

TX_CLK data clock fall (80%–20%)

tMTXF

1.0

—

4.0

—

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit

timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,

the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.

For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

Table 33. MII Receive AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5%.or 2.5 V ± 5%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Notes

RX_CLK clock period 10 Mbps

tMRX

—400

—

RX_CLK clock period 100 Mbps

tMRX

—40

—

RX_CLK duty cycle

tMRXH/tMRX

—

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

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