MPC8544BVTARF datasheet(29/120 Pages) FREESCALE

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MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.4.1

SGMII Transmit AC Timing Specifications

Table 26 provides the SGMII transmit AC timing targets. A source synchronous clock is not provided.

8.4.2

SGMII Receive AC Timing Specifications

Table 27 provides the SGMII receive AC timing specifications. Source synchronous clocking is not

supported. Clock is recovered from the data. Figure 9 shows the SGMII receiver input compliance mask

eye diagram.

Table 26. SGMII Transmit AC Timing Specifications

At recommended operating conditions with XVDD_SRDS2 = 1.0 V ± 5%.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Deterministic jitter

—

0.17

UI p-p

—

Total jitter

—

0.35

UI p-p

—

Unit interval

799.92

800

800.08

VOD fall time (80%–20%)

tfall

—

120

—

VOD rise time (20%–80%)

trise

—

120

—

Notes;

1. Source synchronous clock is not supported.

2. Each UI value is 800 ps ± 100 ppm.

Table 27. SGMII Receiver AC Timing Specifications

At recommended operating conditions with XVDD_SRDS2 = 1.0 V ± 5%.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Deterministic jitter tolerance

0.37

—

UI p-p

Combined deterministic and random jitter

tolerance

JDR

0.55

—

UI p-p

Sinusoidal jitter tolerance

Jsin

0.1

—

UI p-p

Total jitter tolerance

0.65

—

UI p-p

Bit error ratio

BER

—

10-12

——

Unit interval

799.92

800

800.08

AC coupling capacitor

CTX

5—

200

Notes:

1. Measured at receiver.

2. Each UI value is 800 ps ± 100 ppm.

3. The external AC coupling capacitor is required. It’s recommended to be placed near the device transmitter outputs.

MPC8544BVTARF Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc

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