MPC8379CVRALDA datasheet(2/114 Pages) FREESCALE

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MPC8379E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Overview

2.0 dual-role controller, a programmable interrupt controller, dual I2C controllers, a 4-channel DMA

controller, an enhanced secured digital host controller, and a general-purpose I/O port. The block diagram

of the MPC8379E is shown in Figure 1.

Figure 1. MPC8379E Block Diagram and Features

The following features are supported in the MPC8379E:

•

e300c4s core built on Power Architecture™ technology with 32-Kbyte instruction cache and

32-Kbyte data cache, a floating point unit, and two integer units

•

DDR1/DDR2 memory controller supporting a 32/64-bit interface

•

Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MHz operation

•

32-bit local bus interface running up to 133-MHz

•

USB 2.0 (full/high speed) support

•

Power management controller for low-power consumption

•

High degree of software compatibility with previous-generation PowerQUICC processor-based

designs for backward compatibility and easier software migration

•

Optional security engine provides acceleration for control and data plane security protocols

The optional security engine (SEC 3.0) is noted with the extension “E” at the end. It allows CPU-intensive

cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator

provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms.

DMA

PCI

MPC8379E

USB 2.0

Hi-Speed

SATA

PHY

Host

Device

PHY

RGMII, RMII,

eTSEC

RTBI, MII

DDR1/DDR2

SDRAM

Security

Enhanced

e300 Core

32-Kbyte

I-Cache

32-Kbyte

D-Cache

DUART

Dual I2C

Timers

GPIO

SPI

Interrupt

Controller

RGMII, RMII,

eTSEC

RTBI, MII

Local Bus

MPC8379CVRALDA Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc

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