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CY7C024/024A/0241
CY7C025/0251
Document #: 38-06035 Rev. *D
Page 2 of 21
Logic Block Diagram
L
L
L
OEL
A0L
R/WR
UBR
CE R
OE R
CE L
OE L
UB L
UB R
I/O 8L –I/O 15L
INTERRUPT
SEMAPHORE
ARBITRATION
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
SEM L
SEM R
BUSYL
INT L
INTR
M/S
CONTROL
I/O
LB L
LB R
I/O 0L – I/O 7L
R/W L
R/W R
LB
R
CE
R
OE R
A0R
I/O8R I/O15R
BUSYR
I/O 0R I/O 7R
(CY7C025/0251)
A12L
A12R (CY7C025/0251)
[2]
[2]
–
–
ADDRESS
DECODER
A11L
A11R
[3]
[4]
[3]
[4]
Pin Configurations
Figure 1. 84-Pin PLCC (Top View)
Notes
2. BUSY is an output in master mode and an input in slave mode.
3. I/O0 –I/O8 on the CY7C0241/0251.
4. I/O9 –I/O17 on the CY7C0241/0251.
5. A12L on the CY7C025/0251.
6. A12R on the CY7C025/0251.
A7L
A6L
A5L
A4L
A3L
A2L
INTL
BUSYL
M/S
BUSYR
A1R
A2R
I/O8L
I/O9L
I/O10L
I/O11L
I/O12L
I/O13L
I/O15L
VCC
I/O0R
I/O2R
I/O1R
I/O3R
I/O4R
I/O5R
A3R
A4R
A5R
A6R
I/O6R
I/O7R
I/O8R
I/O14L
A1L
A0L
GND
INTR
A0R
GND
GND
VCC
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
CY7C024/024A/025
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