TLC552C

DUAL LINCMOS

™ TIMER

SLFS046 – FEBRUARY 1984 – REVISED MAY 1988

1

POST OFFICE BOX 655303

Rail

Sink 100 mA Typ

Source 10 mA Typ

and MOS

During Output Transitions

NE556; Has Same Pinout

description

The TLC552 is a dual monolithic timing circuit

fabricated using TI LinCMOS

™ process, which

provides full compatibility with CMOS, TTL, and

MOS logic and operation at frequencies up to

2 MHz. Accurate time delays and oscillations are

possible with smaller, less-expensive timing

capacitors than the NE555 because of the high

input impedance. Power consumption is low

across the full range of power supply voltages.

Like the NE556, the TLC552 has a trigger level

approximately one-third of the supply voltage and

a threshold level approximately two-thirds of the

supply voltage. These levels can be altered by use

of the control voltage terminal. When the trigger

input falls below the trigger level, the flip-flop is set

and the output goes high. If the trigger input is

above the trigger level and the threshold input is

above the threshold level, the flip-flop is reset and

the output is low. The reset input can override all other inputs and can be used to initiate a new

timing cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a

low-impedance path is provided between the discharge terminal and ground.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC552 exhibits greatly

reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling

capacitors required by the NE556.

LinCMOS is a trademark of Texas Instruments Incorporated.

Copyright

© 1988, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

DSCH

THRES

CONT

RESET

OUT

TRIG

GND

DSCH

THRES

CONT

RESET

OUT

TRIG

D OR N PACKAGE

(TOP VIEW)

TIMER

# 2

TIMER

# 1

functional block diagram (each timer)

RESET can override TRIG and THRES.

TRIG can override THRES.

OPERATING

TEMPERATURE

RANGE

VT max

at 25

°C

DEVICE

PACKAGE

SUFFIX

SYMBOLIZATION

TLC552C

D,N

0

°C to 70°C

3.8 mV

AVAILABLE OPTIONS

THRES

VDD

R

CONT

R

TRIG

R

R1

R1

S

GND

RESET

OUT

DSCH

The D packages are available taped and reeled. Add the suffix R

to the device type when ordering (i.e., TLC552CDR).