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ACCESS PIN-TIA RECEIVERS FOR 155 MB/S AND 622 MB/S

Typical Applications

The EDR 51xx Series are designed for many applications, including single mode

155 Mb/s (EDR 512x) and 622 Mb/s (EDR 515x) ATM receivers. The EDR 51xx

Series exceed Long Reach OC-3 (EDR 512x) and OC-12 (EDR 515x) SONET

receiver specifications and are ideal for transceiver designs or board level discrete

designs. Applications include receivers for digital cross connects, digital loop

carriers, add/drop multiplexers, optical network units and switches and routers

for LAN and WAN backbones.

External Circuitry

When designing the EDR 51xx Series into an optical receiver, standard high speed

printed circuit board design practices should be observed. For example, bypassing

of the power supply is recommended so as to reduce noise that appears at the

output of the PIN-TIA.

If signal traces are relatively long, use impedance matching techniques to maximize

power transfer from the PIN-TIA to its load: for microstrip design, assume 70 ohms

(EDR 512x) and 60 ohms (EDR 515x) as the output impedance for the PIN-TIA. Note

as well that the output of the PIN-TIA is DC-coupled. Since most applications require

AC-coupled stages, a high-Q RF chip capacitor should be placed on the output of the

module. To eliminate oscillations, the PIN-TIA should be mounted on a circuit board

with a large, low impedance ground plane. All the PIN-TIA leads should be made as

short as possible in order to reduce excess inductances. As a general rule, receiver

bandwidth requirements need only be greater than about 1/3 of the bit rate at which

they are intended to operate. A receiver for a 155 Mb/s system must have a bandwidth

greater than 110 MHz. A receiver for a 622 Mb/s system must have a bandwidth greater

than 415 MHz. On the other hand, any frequency component above 110 MHz for

155 Mb/s systems or above 415 MHz for 622 Mb/s systems contributes excess noise to

the output. The excess noise needlessly reduces the sensitivity of the receiver. The

receiver designer may therefore improve the PIN-TIA sensitivity by placing a low pass

noise filter on the output.

Performance Highlights

The EDR 51x Series offer a sensitivity of better than -36 dBm (EDR 512x) or -30 dBm

(EDR 515x) with appropriate filtering and a minimum overload of 0 dBm (EDR 512x)

or -7 dBm (EDR 515x). This large dynamic range makes these products ideal for both

long and short range applications. A time constant of 4 milliseconds makes the AGC

circuit of the EDR 512x models very stable, even during reception of the longest

streams of high or low logic levels. The EDR 51x Series operate over -40 to +85°C.

The EDR 51x Series provide significant benefits over hybrid designs and 14-pin

receivers. Integration of the TIA with the PIN detector onto the TO-46 header

reduces parasitic capacitances and lead inductances. The TO-52 cap hermetically

seals the hybrid and provides EMI shielding especially from the transmitter

circuit. These advantages improve sensitivity over designs that place the amplifier

outside the capsule and away from the detector. The EDR 51x Series, which have

four pins, are advantageous over 14-pin receivers because they require less board

space and fewer electrical connections. In addition, the EDR 51xx Series operate

from a single power supply, even in the pin-out configuration which provides

photodiode current monitoring. The smaller form factor and the need for a single

power supply make the EDR 51x Series a less expensive, high performance

alternative to other kinds of optical receivers.