UCC28810

UCC28811

Leading Edge Blanking Circuit on the TZE Pin

At startup, the output voltage reflected to the bias winding is well below the 1.7-V threshold that allows the next

pulse to be triggered by TZE transitioning below 1.4 V. Leakage inductance can occur between the windings

causing a leading edge spike on the TZE pin that could potentially trigger the TZE threshold and start the next

pulse before the output winding current has reached 0 A. If this happens to several pulses in a row, the primary

current continues to increase cycle-by-cycle until the transformer saturates and the MOSFET passes it's safe

operating area and is destroyed. The leading edge blanking circuit shown in Figure 21, consists of a charge

pump, level shift, and timed blanking pulse. When the GDRV output to the MOSFET gate switches high, C19 is

discharged to VDD through D18. When the GDRV output transitions low, the base of Q8 is pulled down, and a

timer consisting of C19 and R31 is started.

For the time allowed, current set by R29 is fed through Q8 to the base of Q7, which pulls the TZE pin to GND.

Because the TZE pin sources current at approximately 0.5 V, a 100-

Ω resistor, R28, is used to limit the current

and to allow C18 to be pulled below the TZE clamp by saturating Q7. When the time expires (approximately 1

µs

in the schematic shown in Figure 21) C18 is charged by R27 to the bias winding voltage. When this voltage

charges above 1.7 V, the PWM latch is ready to be set by the TZE pin falling below 1.4 V, and the leakage

inductance spike has been effectively blanked. When the pulse width is very small, it is possible that the time set

by the blanking circuit is longer than the secondary conduction time. When this happens, the next oscillation of

the winding is detected and the valley causes the main switch to fire. If no falling edge is detected, or the TZE pin

never rises above 1.7 V, then a 400-

µs timer triggers a new pulse.

Figure 21. Leading Edge Blanking Circuit on TZE

18

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