M30620FCAFP datasheet(377/615 Pages) RENESAS

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Clock-Synchronous Serial I/O

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-60

In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table

2.4.1. Operations of the circled items are described below. Figure 2.4.7 shows the operation timing, and

Figures 2.4.8 and 2.4.9 show the set-up procedures.

2.4.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode)

Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is

_______ _______

selected, UART1 CTS/RTS function can not be utilized. Set the UART1 CTS/RTS disable bit to “1”.

Note 2: UART2 only.

(1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit

buffer register makes data transmissible status ready.

________

_______

(2) When input to the CTSi pin goes to “L” level, transmission starts (the CTSi pin must be

controlled on the reception side).

(3) In synchronization with the first falling edge of the transfer clock, transmission data held in the

UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the

UARTi transmit interrupt request bit goes to “1”. Also, the first bit of the transmission data is

transmitted from the TxDi pin. Then the data is transmitted bit by bit from the lower order in

synchronization with the falling edges.

(4) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”,

which indicates that transmission is completed. The transfer clock stops at “H” level.

(5) If the next transmission data is set in the UARTi transmit buffer register while transmission is

in progress (before the eighth bit has been transmitted), the data is transmitted in succession.

Operation

Item

Set-up

Transfer clock

source

CLK polarity

Internal clock (f1 / f8 / f32)

External clock (CLKi pin)

CTS function

CTS function enabled

CTS function disabled

Output transmission data at

the falling edge of the

transfer clock

Output transmission data at

the rising edge of the

transfer clock

Transmission

interrupt factor

Transmission buffer empty

Transmission complete

Output transfer clock

to multiple pins

(Note 1)

Not selected

Selected

Transfer clock

LSB first

MSB first

Data logic select

function

(Note 2)

No reverse

Reverse

TXD, RXD I/O

polarity reverse bit

(Note 2)

No reverse

Reverse

Table 2.4.1. Choosed functions

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