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H8SX1663 Datasheet(PDF) 776 Page - Renesas Technology Corp |
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H8SX1663 Datasheet(HTML) 776 Page - Renesas Technology Corp |
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776 / 1158 page ![]() Section 15 Serial Communication Interface (SCI, IrDA, CRC) Rev.1.00 Jun. 07, 2006 Page 724 of 1102 REJ09B0294-0100 For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 15.26. Therefore, data in the start character in the figure is H'3B. When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR. Write 0 to the O/ E bit in SMR in order to use even parity, which is prescribed by the smart card standard. Ds AZ Z A A A Z AA A (Z) (Z) state D7 D6 D5 D4 D3 D2 D1 D0 Dp Figure 15.27 Inverse Convention (SDIR = SINV = O/ E = 1) For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively and data is transferred with MSB-first as the start character, as shown in figure 15.27. Therefore, data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity, which is prescribed by the smart card standard, and corresponds to state Z. Since the SNIV bit of this LSI only inverts data bits D7 to D0, write 1 to the O/ E bit in SMR to invert the parity bit in both transmission and reception. 15.7.3 Block Transfer Mode Block transfer mode is different from normal smart card interface mode in the following respects. • Even if a parity error is detected during reception, no error signal is output. Since the PER bit in SSR is set by error detection, clear the PER bit before receiving the parity bit of the next frame. • During transmission, at least 1 etu is secured as a guard time after the end of the parity bit before the start of the next frame. • Since the same data is not re-transmitted during transmission, the TEND flag is set 11.5 etu after transmission start. • Although the ERS flag in block transfer mode displays the error signal status as in normal smart card interface mode, the flag is always read as 0 because no error signal is transferred. |
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