H8SX1663 datasheet(757/1158 Pages) RENESAS

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Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Rev.1.00 Jun. 07, 2006 Page 705 of 1102

REJ09B0294-0100

15.4.6

Serial Data Reception (Asynchronous Mode)

Figure 15.11 shows an example of the operation for reception in asynchronous mode. In serial

reception, the SCI operates as described below.

1. The SCI monitors the communication line, and if a start bit is detected, performs internal

synchronization, stores receive data in RSR, and checks the parity bit and stop bit.

2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR

is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this

time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF

flag remains to be set to 1.

3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to

RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.

4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive

data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt

request is generated.

5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is

transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is

generated. Because the RXI interrupt processing routine reads the receive data transferred to

RDR before reception of the next receive data has finished, continuous reception can be

enabled.

RDRF

FER

1 frame

0/1

Data

Start

bit

Parity

bit

Stop

bit

Start

bit

Data

Parity

bit

Stop

bit

ERI interrupt request

generated by framing

error

Idle state

(mark state)

RDR data read and RDRF

flag cleared to 0 in RXI

interrupt processing routine

RXI interrupt

request

generated

Figure 15.11 Example of SCI Operation for Reception

(Example with 8-Bit Data, Parity, One Stop Bit)

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