H8SX1663 datasheet(718/1158 Pages) RENESAS

718 / 1158 page

Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Rev.1.00 Jun. 07, 2006 Page 666 of 1102

REJ09B0294-0100

15.3.6

Serial Control Register (SCR)

SCR is a register that enables/disables the following SCI transfer operations and interrupt requests,

and selects the transfer clock source. For details on interrupt requests, see section 15.9, Interrupt

Sources. Some bits in SCR have different functions in normal mode and smart card interface

mode.

• When SMIF in SCMR = 0

TIE

R/W

RIE

R/W

MPIE

R/W

TEIE

R/W

CKE1

R/W

CKE0

R/W

Bit

Bit Name

Initial Value

R/W

• When SMIF in SCMR = 1

TIE

R/W

RIE

R/W

MPIE

R/W

TEIE

R/W

CKE1

R/W

CKE0

R/W

Bit

Bit Name

Initial Value

R/W

Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):

Bit

Bit Name

Initial

Value

R/W

Description

TIE

R/W

Transmit Interrupt Enable

When this bit is set to 1, a TXI interrupt request is

enabled.

A TXI interrupt request can be cancelled by reading 1

from the TDRE flag and then clearing the flag to 0, or by

clearing the TIE bit to 0.

RIE

R/W

Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt requests

are enabled.

RXI and ERI interrupt requests can be cancelled by

reading 1 from the RDRF, FER, PER, or ORER flag and

then clearing the flag to 0, or by clearing the RIE bit to 0.

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