H8SX1663 datasheet(667/1158 Pages) RENESAS

667 / 1158 page

Section 12 8-Bit Timers (TMR)

Rev.1.00 Jun. 07, 2006 Page 615 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

CMIEA

R/W

Compare Match Interrupt Enable A

Selects whether CMFA interrupt requests (CMIA) are

enabled or disabled when the CMFA flag in TCSR is set

to 1. *

0: CMFA interrupt requests (CMIA) are disabled

1: CMFA interrupt requests (CMIA) are enabled

OVIE

R/W

Timer Overflow Interrupt Enable*

Selects whether OVF interrupt requests (OVI) are

enabled or disabled when the OVF flag in TCSR is set to

0: OVF interrupt requests (OVI) are disabled

1: OVF interrupt requests (OVI) are enabled

CCLR1

CCLR0

R/W

Counter Clear 1 and 0*

These bits select the method by which TCNT is cleared.

00: Clearing is disabled

01: Cleared by compare match A

10: Cleared by compare match B

11: Cleared at rising edge (TMRIS in TCCR is cleared to

0) of the external reset input or when the external

reset input is high (TMRIS in TCCR is set to 1) *

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0*

These bits select the clock input to TCNT and count

condition. See table 12.2.

Notes: 1. To use an external reset or external clock, the DDR and ICR bits in the corresponding

pin should be set to 0 and 1, respectively. For details, see section 9, I/O Ports.

2. In unit 2 and unit 3, one interrupt signal is used for CMIEB or CMIEA. For details, see

section 12.7, Interrupt Sources.

3. Available only in unit 0 and unit 1

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