HD6432138SW datasheet(268/1061 Pages) RENESAS

268 / 1061 page

Section 8 I/O Ports

Rev. 4.00 Jun 06, 2006 page 214 of 1004

REJ09B0301-0400

Port 4 Data Direction Register (P4DDR)

P47DDR

P46DDR

P45DDR

P44DDR

P43DDR

P40DDR

P42DDR

P41DDR

Bit

Initial value

Read/Write

P4DDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port 4. P4DDR cannot be read; if it is, an undefined value will be returned.

When a bit in P4DDR is set to 1, the corresponding pin functions as an output port, and when

cleared to 0, as an input port.

P4DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in

software standby mode. As 14-bit PWM and SCI2 are initialized in software standby mode, the

pin states are determined by the TMR0, TMR1, HIF, IIC1, P4DDR, and P4DR specifications.

Port 4 Data Register (P4DR)

P47DR

R/W

P46DR

R/W

P45DR

R/W

P44DR

R/W

P43DR

R/W

P40DR

R/W

P42DR

R/W

P41DR

R/W

Bit

Initial value

Read/Write

P4DR is an 8-bit readable/writable register that stores output data for the port 4 pins (P47 to P40).

If a port 4 read is performed while P4DDR bits are set to 1, the P4DR values are read directly,

regardless of the actual pin states. If a port 4 read is performed while P4DDR bits are cleared to 0,

the pin states are read.

P4DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in

software standby mode.

8.5.3

Pin Functions

Port 4 pins also function as 14-bit PWM output pins (PWX1, PWX0), 8-bit timer 0 and 1 (TMR0,

TMR1) I/O pins (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1), timer connection I/O pins

(CSYNCI, HSYNCI, HSYNCO), SCI2 I/O pins (TxD2, RxD2, SCK2), IrDA interface I/O pins

(IrTxD, IrRxD), host interface output pins (HIRQ12, HIRQ1, HIRQ11), and the IIC1 I/O pin

(SDA1). The port 4 pin functions are shown in table 8.10.

HD6432138SW Datasheet(PDF) 268 Page - Renesas Technology Corp

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