HD6432138SW datasheet(156/1061 Pages) RENESAS

156 / 1061 page

Section 5 Interrupt Controller

Rev. 4.00 Jun 06, 2006 page 102 of 1004

REJ09B0301-0400

5.1.2

Block Diagram

A block diagram of the interrupt controller is shown in figure 5.1.

SYSCR

NMI input

IRQ input

Internal interrupt

requests

SWDTEND to IICI1

INTM1 INTM0

NMIEG

NMI input unit

IRQ input unit

ISR

ISCR

IER

ICR

Interrupt controller

Priority

determination

Interrupt

request

Vector

number

I, UI

CCR

CPU

IRQ sense control register

IRQ enable register

IRQ status register

Interrupt control register

System control register

Legend:

ISCR:

IER:

ISR:

ICR:

SYSCR:

Figure 5.1 Block Diagram of Interrupt Controller

5.1.3

Pin Configuration

Table 5.1 summarizes the pins of the interrupt controller.

Table 5.1

Interrupt Controller Pins

Name

Symbol

I/O

Function

Nonmaskable interrupt

NMI

Input

Nonmaskable external interrupt; rising or

falling edge can be selected

External interrupt

requests 7 to 0

IRQ7 to IRQ0 Input

Maskable external interrupts; rising, falling, or

both edges, or level sensing, can be selected.

Key input interrupt

requests 7 to 0

KIN7 to KIN0 Input

Maskable external interrupts: falling edge or

level sensing can be selected.

HD6432138SW Datasheet(PDF) 156 Page - Renesas Technology Corp

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