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HD6432138SW Datasheet(PDF) 1026 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 1026 Page - Renesas Technology Corp |
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1026 / 1061 page ![]() Appendix C I/O Port Block Diagrams Rev. 4.00 Jun 06, 2006 page 972 of 1004 REJ09B0301-0400 D R QD P42DR C Reset R Q P42DDR C Reset Hardware standby WP4D *1 *2 WP4 SCI2 Input enable Clock output SDA1 output SDA1 input Transmit enable Output enable Clock output IIC1 8-bit timer 0 Reset input P42 RP4 Legend: WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 Notes: 1. Output enable signal 2. Open drain control signal Figure C.8 Port 4 Block Diagram (Pin P42) |
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