HD6432138SW datasheet(1007/1061 Pages) RENESAS

1007 / 1061 page

Appendix B Internal I/O Registers

Rev. 4.00 Jun 06, 2006 page 953 of 1004

REJ09B0301-0400

TCSR1—Timer Control/Status Register 1

H'FFEA

WDT1

OVF

R/(W)*1

WT/

R/W

TME

R/W

PSS

R/W

RST/

NMI

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

Read/Write

TCSR1

Clock select 2 to 0

PSS

Clock

CKS2

CKS1

CKS0

Notes: 1.

φ/2

φ/64

φ/128

φ/512

φ/2048

φ/8192

φ/32768

φ/131072

φSUB/2

φSUB/4

φSUB/8

φSUB/16

φSUB/32

φSUB/64

φSUB/128

φSUB/256

Reset or NMI

NMI interrupt requested

Internal reset requested

Prescaler select*

TCNT counts on a

φ-based prescaler (PSM) scaled clock

TCNT counts on a

φSUB-based prescaler (PSS) scaled clock

Timer enable

TCNT is initialized to H'00 and halted

TCNT counts

Timer mode select

Interval timer mode: Interval timer interrupt request (WOVI)

sent to CPU when TCNT overflows

Watchdog timer mode: Reset or NMI interrupt request sent

to CPU when TCNT overflows

Overflow flag

[Clearing conditions]

• When 0 is written in the TME bit

• When 0 is written in OVF after reading TCSR when OVF = 1

[Setting condition]

When TCNT overflows from H'FF to H'00

When internal reset request is selected in watchdog timer mode, OVF is cleared

automatically by an internal reset after being set

Only 0 can be written, to clear the flag.

For operation control when a transition is made to power-down mode, see section 24.2.3, Timer Control/Status Register (TCSR).

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