HD6432138SW datasheet(947/1061 Pages) RENESAS

947 / 1061 page

Appendix B Internal I/O Registers

Rev. 4.00 Jun 06, 2006 page 893 of 1004

REJ09B0301-0400

MRB—DTC Mode Register B

H'EC00–H'EFFF

DTC

CHNE

Undefined

—

DISEL

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Bit

Initial value

Read/Write

DTC interrupt select

0 After a data transfer ends, the CPU interrupt is

disabled unless the transfer counter is 0

1 After a data transfer ends, the CPU interrupt is

enabled

DTC chain transfer enable

0 End of DTC data transfer

1 DTC chain transfer

SAR—DTC Source Address Register

H'EC00–H'EFFF

DTC

Unde-

fined

—

Bit

Initial value

Read/Write

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

- - -

Specifies DTC transfer data source address

DAR—DTC Destination Address Register

H'EC00–H'EFFF

DTC

Unde-

fined

—

Bit

Initial value

Read/Write

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

- - -

Specifies DTC transfer data destination address

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