HD6432138SW datasheet(823/1061 Pages) RENESAS

823 / 1061 page

Section 25 Electrical Characteristics

Rev. 4.00 Jun 06, 2006 page 769 of 1004

REJ09B0301-0400

(1) Clock Timing

Table 25.31 shows the clock timing. The clock timing specified here covers clock (

φ) output and

clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times.

For details of external clock input (EXTAL pin and EXCL pin) timing, see section 23, Clock

Pulse Generator.

Table 25.31 Clock Timing

Condition A: V

CC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency,

a = –20 to +75°C (regular specifications),

a = –40 to +85°C (wide-range specifications)

Condition B: V

CC = 4.0 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency,

a = –20 to +75°C (regular specifications),

a = –40 to +85°C (wide-range specifications)

Condition C: V

CC = 2.7 V to 5.5 V (mask ROM version), VCC = 3.0 V to 5.5 V (F-ZTAT version),

SS = 0 V, φ = 2 MHz to maximum operating frequency, Ta = –20 to +75°C

Condition A

Condition B

Condition C

20 MHz

16 MHz

10 MHz

Item

Symbol

Min

Max

Min

Max

Min

Max

Unit

Test

Conditions

Clock cycle time

cyc

500

62.5

500

100

500

Figure 25.5

Clock high pulse

width

—

Clock low pulse

width

—

Clock rise time

—

Clock fall time

—

Oscillation settling

time at reset

(crystal)

OSC1

—

Figure 25.6

Figure 25.7

Oscillation settling

time in software

standby (crystal)

OSC2

—

External clock

output stabilization

delay time

DEXT

500

—

500

—

500

—

µs

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