HD6432138SW datasheet(756/1061 Pages) RENESAS

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Section 24 Power-Down State

Rev. 4.00 Jun 06, 2006 page 702 of 1004

REJ09B0301-0400

24.11

Direct Transition

24.11.1

Overview of Direct Transition

There are three operating modes in which the CPU executes programs: high-speed mode, medium-

speed mode, and subactive mode. A transition between high-speed mode and subactive mode

without halting the program is called a direct transition. A direct transition can be carried out by

setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction. After the transition,

direct transition exception handling is started.

Direct Transition from High-Speed Mode to Subactive Mode: If a SLEEP instruction is

executed in high-speed mode while the SSBY bit in SBYCR, the LSON bit and DTON bit in

LPWRCR, and the PSS bit in TSCR (WDT1) are all set to 1, a transition is made to subactive

mode.

Direct Transition from Subactive Mode to High-Speed Mode: If a SLEEP instruction is

executed in subactive mode while the SSBY bit in SBYCR is set to 1, the LSON bit is cleared to 0

and the DTON bit is set to 1 in LPWRCR, and the PSS bit in TSCR (WDT1) is set to 1, after the

elapse of the time set in bits STS2 to STS0 in SBYCR, a transition is made to directly to high-

speed mode.

24.12

Usage Notes

1. When making a transition to subactive mode or watch mode, set the DTC to enter module stop

mode (write 1 to the relevant bits in MSTPCR), and then read the relevant bits to confirm that

they are set to 1 before mode transition. Do not clear module stop mode (write 0 to the relevant

bits in MSTPCR) until a transition from subactive mode to high-speed mode or medium-speed

mode has been performed.

If a DTC activation source occurs in sub-active mode, the DTC will be activated only after

module stop mode has been cleared and high-speed mode or medium-speed mode has been

entered.

2. The on-chip peripheral modules (DTC and TPU) which halt operation in subactive mode

cannot clear an interrupt in subactive mode. Therefore, if a transition is made to sub-active

mode while an interrupt is requested, the CPU interrupt source cannot be cleared. Disable the

interrupts of each on-chip peripheral module before executing a SLEEP instruction to enter

subactive mode or watch mode.

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