HD6432138SW datasheet(750/1061 Pages) RENESAS

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Section 24 Power-Down State

Rev. 4.00 Jun 06, 2006 page 696 of 1004

REJ09B0301-0400

24.6.3

Setting Oscillation Settling Time after Clearing Software Standby Mode

Bits STS2 to STS0 in SBYCR should be set as described below.

Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the

oscillation settling time).

Table 24.5 shows the standby times for different operating frequencies and settings of bits STS2 to

STS0.

Table 24.5

Oscillation Settling Time Settings

STS2 STS1 STS0 Standby Time

MHz

Unit

8192 states

0.41

0.51

0.65

0.8

1.0

1.3

2.0

4.1

16384 states

0.82

1.0

1.3

1.6

2.0

2.7

4.1

8.2

32768 states

1.6

2.0

2.7

3.3

4.1

5.5

8.2

16.4

65536 states

3.3

4.1

5.5

6.6

8.2

10.9 16.4

32.8

131072 states

6.6

8.2

10.9

13.1 16.4

21.8

32.8

65.5

262144 states

13.1 16.4

21.8

26.2

32.8

43.6

65.6

131.2

Reserved

———

——

16 states*

0.8

1.0

1.3

1.6

2.0

1.7

4.0

8.0

µs

: Recommended time setting

Note:

Do not used this setting in the on-chip flash memory version.

Using an External Clock: Any value can be set. Normally, use of the minimum time is

recommended.

24.6.4

Software Standby Mode Application Example

Figure 24.3 shows an example in which a transition is made to software standby mode at the

falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI

pin.

In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling

edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set

to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.

Software standby mode is then cleared at the rising edge on the NMI pin.

HD6432138SW Datasheet(PDF) 750 Page - Renesas Technology Corp

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