HD6432138SW datasheet(744/1061 Pages) RENESAS

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Section 24 Power-Down State

Rev. 4.00 Jun 06, 2006 page 690 of 1004

REJ09B0301-0400

Bit 4—Prescaler Select (PSS): Selects the WDT1 TCNT input clock.

This bit also controls the operation in a power-down mode transition. The operating mode to

which a transition is made after execution of a SLEEP instruction is determined in combination

with other control bits.

For details, see the description of Clock Select 2 to 0 in section 14.2.2, Timer Control/Status

Bit 4

PSS

Description

TCNT counts

φ-based prescaler (PSM) divided clock pulses

When a SLEEP instruction is executed in high-speed mode or medium-speed mode,

a transition is made to sleep mode or software standby mode

(Initial value)

TCNT counts

φSUB-based prescaler (PSM) divided clock pulses

When a SLEEP instruction is executed in high-speed mode or medium-speed mode,

a transition is made to sleep mode, watch mode*, or subactive mode*

When a SLEEP instruction is executed in subactive mode, a transition is made to

subsleep mode, watch mode, or high-speed mode

Note:

When a transition is made to watch mode or subactive mode, high-speed mode must

be set.

24.2.4

Module Stop Control Register (MSTPCR)

MSTP15

R/W

Bit

Initial value

Read/Write

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRH

MSTPCRL

MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control.

MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

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