HD6432138SW datasheet(708/1061 Pages) RENESAS

708 / 1061 page

Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version)

Rev. 4.00 Jun 06, 2006 page 654 of 1004

REJ09B0301-0400

22.9

Interrupt Handling when Programming/Erasing Flash Memory

All interrupts, including NMI input is disabled when flash memory is being programmed or erased

(when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode*

to give priority to the program or erase operation. There are three reasons for this:

1. Interrupt during programming or erasing might cause a violation of the programming or

erasing algorithm, with the result that normal operation could not be assured.

2. In the interrupt exception handling sequence during programming or erasing, the vector would

not be read correctly*

2, possibly resulting in MCU runaway.

3. If interrupt occurred during boot program execution, it would not be possible to execute the

normal boot mode sequence.

For these reasons, in on-board programming mode alone there are conditions for disabling

interrupt, as an exception to the general rule. However, this provision does not guarantee normal

erasing and programming or MCU operation. All interrupt requests, including NMI input, must

therefore be disabled inside and outside the MCU when programming or erasing flash memory.

Interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1.

Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming

control program has completed programming.

2. The vector may not be read correctly in this case for the following two reasons:

•

If flash memory is read while being programmed or erased (while the P or E bit is

set in FLMCR1), correct read data will not be obtained (undetermined values will

be returned).

•

If the interrupt entry in the vector table has not been programmed yet, interrupt

exception handling will not be executed correctly.

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