HD6432138SW datasheet(692/1061 Pages) RENESAS

692 / 1061 page

Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version, H8S/2134 F-ZTAT A-Mask Version)

Rev. 4.00 Jun 06, 2006 page 638 of 1004

REJ09B0301-0400

Table 22.5

Flash Memory Erase Blocks

Block (Size)

Address

EB0 (1 kbyte)

H'(00)0000 to H'(00)03FF

EB1 (1 kbyte)

H'(00)0400 to H'(00)07FF

EB2 (1 kbyte)

H'(00)0800 to H'(00)0BFF

EB3 (1 kbytes)

H'(00)0C00 to H'(00)0FFF

EB4 (28 kbytes)

H'(00)1000 to H'(00)7FFF

EB5 (16 kbytes)

H'(00)8000 to H'(00)BFFF

EB6 (8 kbytes)

H'(00)C000 to H'(00)DFFF

EB7 (8 kbytes)

H'00E000 to H'00FFFF

EB8 (32 kbytes)

H'010000 to H'017FFF

EB9 (32 kbytes)

H'018000 to H'01FFFF

22.5.4

Serial Timer Control Register (STCR)

Bit

543210

—

IICX1

IICX0

IICE

FLSHE

—

ICKS1

ICKS0

Initial value

000000

Read/Write

R/W

STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode

(when the on-chip IIC option is included), and on-chip flash memory, and also selects the TCNT

input clock. For details on functions not related to on-chip flash memory, see section 3.2.4, Serial

Timer Control Register (STCR), and descriptions of individual modules. If a module controlled by

STCR is not used, do not write 1 to the corresponding bit.

STCR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7—Reserved: Do not set to 1.

Bits 6 to 4—I

2C Control (IICX1, IICX0, IICE): These bits control the operation of the I2C bus

interface. For details, see section 16, I

2C Bus Interface [H8S/2138 Group Option].

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