HD6432138SW datasheet(654/1061 Pages) RENESAS

654 / 1061 page

Section 21 ROM (Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT)

Rev. 4.00 Jun 06, 2006 page 600 of 1004

REJ09B0301-0400

21.7

Programming/Erasing Flash Memory

In the on-board programming modes, flash memory programming and erasing is performed by

software, using the CPU. There are four flash memory operating modes: program mode, erase

mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by

setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1.

The flash memory cannot be read while being programmed or erased. Therefore, the program that

controls flash memory programming/erasing (the programming control program) should be

located and executed in on-chip RAM or external memory.

Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, EV, PV, E, and P bits in

FLMCR1, and the ESU and PSU bits in FLMCR2, is executed by a program in flash

memory.

2. Perform programming in the erased state. Do not perform additional programming on

previously programmed addresses.

21.7.1

Program Mode

Follow the procedure shown in the program/program-verify flowchart in figure 21.12 to write data

or programs to flash memory. Performing program operations according to this flowchart will

enable data or programs to be written to flash memory without subjecting the device to voltage

stress or sacrificing program data reliability. Programming should be carried out 32 bytes at a

time.

The wait times (x, y, z,

α, β, γ, ε, η) after setting/clearing individual bits in flash memory control

registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of writes (N) are shown in

section 25, Electrical Characteristics, Flash Memory Characteristics.

Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control

area, and the 32-byte data in the reprogram data area written consecutively to the write addresses.

The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0,

or H'E0. Thirty-two consecutive byte data transfers are performed. The program address and

program data are latched in the flash memory. A 32-byte data transfer must be performed even if

writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses.

Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.

Set a value greater than (y + z +

α + β) µs as the WDT overflow period. After this, preparation for

program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the

elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in

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