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HD6432138SW Datasheet(PDF) 615 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 615 Page - Renesas Technology Corp |
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615 / 1061 page  Section 19 A/D Converter Rev. 4.00 Jun 06, 2006 page 561 of 1004 REJ09B0301-0400 19.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, but the data bus to the bus master is only 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 19.2 shows the data flow for ADDR access. Bus master (H'AA) ADDRnH (H'AA) ADDRnL (H'40) Lower byte read ADDRnH (H'AA) ADDRnL (H'40) TEMP (H'40) TEMP (H'40) (n = A to D) (n = A to D) Module data bus Module data bus Bus interface Upper byte read Bus master (H'40) Bus interface Figure 19.2 ADDR Access Operation (Reading H'AA40) |
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