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HD6432138SW Datasheet(PDF) 509 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 509 Page - Renesas Technology Corp |
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509 / 1061 page ![]() Section 16 I 2C Bus Interface [H8S/2138 Group Option] Rev. 4.00 Jun 06, 2006 page 455 of 1004 REJ09B0301-0400 Section 16 I 2C Bus Interface [H8S/2138 Group Option] A two-channel I 2C bus interface is available as an option in the H8S/2138 Group. The I2C bus interface is not available for the H8S/2134 Group. Observe the following notes when using this option. 1. For mask-ROM versions, a W is added to the part number in products in which this optional function is used. Examples: HD6432137SW 2. The product number is identical for F-ZTAT versions. However, be sure to inform your Renesas sales representative if you will be using this option. 16.1 Overview A two-channel I 2C bus interface is available for the H8S/2138 Group as an option. The I2C bus interface conforms to and provides a subset of the Philips I 2C bus (inter-IC bus) interface functions. The register configuration that controls the I 2C bus differs partly from the Philips configuration, however. Each I 2C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer data, saving board and connector space. 16.1.1 Features • Selection of addressing format or non-addressing format I2C bus format: addressing format with acknowledge bit, for master/slave operation Serial format: non-addressing format without acknowledge bit, for master operation only • Conforms to Philips I2C bus interface (I2C bus format) • Two ways of setting slave address (I2C bus format) • Start and stop conditions generated automatically in master mode (I2C bus format) • Selection of acknowledge output levels when receiving (I2C bus format) • Automatic loading of acknowledge bit when transmitting (I2C bus format) • Wait function in master mode (I2C bus format) A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. |
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