M38260EBFS datasheet(21/91 Pages) RENESAS

21 / 91 page

Rev.1.00

Sep 06, 2006

page 21 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

Fig. 17 Port block diagram (4)

(18) Port P61

(19) Port P62

(20) Port P63

Serial I/O2 output

Serial I/O2 transmit end signal

Serial I/O2 synchronous clock selection bit

Serial I/O2 port selection bit

Pull-up control

Analog input pin selection bit

A/D converter input

P61/SOUT2 P-channel output disable bit

(21) COM0–COM3

(22) SEG0–SEG17

VL3

VL2

VL1

VSS

VL2/VL3

VL1/VSS

(23) Port P70

INT0 input

Serial I/O2 synchronous clock

selection bit

Serial I/O2 clock output

Serial I/O2 clock input

Serial I/O2 port selection bit

Synchronous clock output pin

selection bit

A/D converter input

Serial I/O2 clock output

A/D converter input

Direction

Port latch

Data bus

Pull-up control

Direction

Port latch

Data bus

Analog input pin selection bit

Pull-up control

Direction

Port latch

Data bus

Analog input pin selection bit

Serial I/O2 synchronous clock selection bit

Serial I/O2 port selection bit

Data bus

The gate input signal of each

transistor is controlled by the LCD

duty ratio and the bias value.

The voltage applied to the sources of P-

channel and N-channel transistors is the

controlled voltage by the bias value.

Synchronous clock output pin selection

bit

M38260EBFS Datasheet(PDF) 21 Page - Renesas Technology Corp

M38260EBFS Datasheet(HTML) 21 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Datasheet Download

Link URL