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M95512WDW6TP Datasheet(PDF) 6 Page - STMicroelectronics |
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M95512WDW6TP Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 39 page ![]() Description M95512-W, M95512-R 6/39 1 Description These electrically erasable programmable memory (EEPROM) devices are accessed by a high speed SPI-compatible bus. The memory array is organized as 65536 x 8 bit. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 1. The device is selected when Chip Select (S) is taken low. Communications with the device can be interrupted using Hold (HOLD). Figure 1. Logic diagram Table 1. Signal names Signal name Function Direction C Serial Clock Input D Serial Data Input Input Q Serial Data Output Output S Chip Select Input W Write Protect Input HOLD Hold Input VCC Supply voltage VSS Ground AI01789C S VCC M95xxx HOLD VSS W Q C D |
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