ST24LC21 datasheet(13/18 Pages) STMICROELECTRONICS

13 / 18 page

Sequential Read. This mode can be initiated with

either a Current Address Read or a Random Ad-

dress Read. However, in this case the master

DOES acknowledge the data byte output and the

memory continues to output the next byte in se-

quence. To terminate the stream of bytes, the

master must NOT acknowledge the last byte out-

put, but MUST generate a STOP condition. The

output data is from consecutive byte addresses,

with the internal byte address counter automat-

ically incremented after each byte output. After a

count of the last memory address, the address

counter will ’roll- over’ and the memory will continue

to output data.

Acknowledge in Read Mode. In all read modes

the ST24LC21 wait for an acknowledge during the

9th bit time. If the master does not pull the SDA line

low during this time, the ST24LC21 terminate the

data transfer and switches to a standby state.

BYTE WRITE

CONTROL

BYTE

WORD ADDR

DATA

PAGE WRITE

WORD ADD n

DATA n

DATA n + 1

AI01505

ACK

VCLK

CONTROL

BYTE

DATA n + 7

ACK

Figure 11. Inhibited Write when VCLK = 0

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ST24LC21

ST24LC21 Datasheet(PDF) 13 Page - STMicroelectronics