ST18952 datasheet(21/67 Pages) STMICROELECTRONICS

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ST18952

DMA Controller

The DMA controller manages data transfer between memories and external peripherals and

has the following features:

• four independent DMA channels

• transfers on X / Y / I spaces (simultaneous transfers on X and Y spaces)

• cycle stealing operation:

•

3 cycles for a single data transfer (+1cycle for transfers on I space)

•

(n+2) cycles for an n-data block transfer (+1cycle for transfers on I space)

• each channel has:

•

3 signals: request (DMARQ), acknowledge (DMACK), interrupt request (DIT)

•

4x16 bit registers for block transfer facilities

• fixed priority between the four channels (highest channel 0, lowest channel 3)

The DMA controller DMARQ0-3 inputs and DMACK0-3 outputs are available as primary

inputs, in the case of SIO inhibition. This is set by the DMAR register (see ”DMAR: DMA

management register” on page 44).

Figure 7.1

DMA controller

D950Core

INTERR UPT

CONTROLLER

PERIPHERAL

RESET

AS-D SP

HOLD

HOLDACK

INCY CLE

DMA CONTROLLER PERIPHERAL

DMARQ0

DMARQ1

DMARQ2

DMARQ3

DMACK0

DMACK1

DMACK2

DMACK3

DTACK

DIP_ENA

XA XD

IRD

IWR

IBS

XR D

XW R

XB S

YRD

YWR

YBS

DIT 0

DIT1

DIT2

DIT3

DIT_AND

CLK

DMA_CLK

ST18952 Datasheet(PDF) 21 Page - STMicroelectronics

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