4/15

ST16-19RFRDCS

FSD_CHIPSET_B/0104VP2

Figure 3 FPGA read access chronogram for last byte

Before sending the last byte the FPGA takes the Rx_fifo_empty line high to indicate to the MCU that this

is the last data.

1.3.5 MCU interface timings

The following board provides interface timings (cf previous chronogram)

Table 1 : Interface timing

Timing

Parameter

Min. (ns)

Max. (ns)

t0

Rx_irq_eof to Mic_Strb_b Transition

0

t1

Mic_Ctrl_Data, Mic_RW (and Mic_Data in writing) Setup Time before

Mic_Strb_b Low Transition

0

t2

Mic_Ctrl_Data, Mic_RW (and Mic_Data in writing) Hold Time before

Mic_Strb_b High Transition

0

t3

Mic_Strb_b Width Low (Activ)

240

t4

Mic_Strb_b Width High (Inactiv)

80

t5

Mic_Strb_b Activ to Valid Data in Reading

240

t6

Mic_Strb_b Inactiv to Tri-States Data in Reading

20

Acquisition of the last byte

t6

t4

t3

Mic_Ctrl_Data

Mic_RW

Mic_Strb_b

Mic_Data(7:0)

Rx_fifo_empty

Rx_irq_eof

Tx_fifo_empty

Tx_start

t1

t2

t0

t5