NRF24L01P-R datasheet(52/78 Pages) NORDIC

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nRF24L01+ Product Specification

Note:

The 3 bit pipe information in the STATUS register is updated during the IRQ pin high to low

transition. The pipe information is unreliable if the STATUS register is read during an IRQ pin

high to low transition.

8.3.2

SPI timing

SPI operation and timing is shown in Figure 26. to Figure 28. and in Table 22. to Table 27.. nRF24L01+

must be in a standby or power down mode before writing to the configuration registers.

In Figure 26. to Figure 28. the following abbreviations are used:

Table 21. Abbreviations used in Figure 26. to Figure 28.

Figure 26. SPI read operation

Figure 27. SPI write operation

Figure 28. SPI NOP timing diagram

Abbreviation

Description

SPI command bit

STATUS register bit

Data Bit (Note: LSByte to MSByte, MSBit in each byte first)

D1 5

D1 4

D1 3

D1 2

D1 1

D1 0

CSN

SCK

MOSI

MISO

D1 5

D1 4

D1 3

D1 2

D1 1

D1 0

CSN

SCK

MOSI

MISO

Tcdz

Tcd

Tcsd

Tdh

Tdc

Tcch

Tcl

Tch

Tcc

Tch

Tcwh

CSN

SCK

MOSI

MISO

NRF24L01P-R Datasheet(PDF) 52 Page - Nordic Semiconductor

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