STPM12ATR datasheet(12/45 Pages) STMICROELECTRONICS

12 / 45 page

Terminology

STPM11/12/13/14

12/45

Terminology

5.1

Measurement error

The error associated with the energy measured by STPM1X is defined as:

Percentage Error = [STPM1X (reading) - True Energy] / True Energy

5.2

ADC offset error

This is the error due to the DC component associated with the analog inputs of the A/D

converters. Due to the internal automatic DC offset cancellation, the STPM1X measurement

is not affected by DC components in voltage and current channel. The DC offset

cancellation is implemented in the DSP.

5.3

Gain error

The gain error is gain due to the signal channel gain amplifiers. This is the difference

between the measured ADC code and the ideal output code. The difference is expressed as

a percentage of the ideal code.

5.4

Power supply DC and AC rejection

This parameter quantifies the STPM1X measurement error as a percentage of the reading

when the power supplies are varied. For the PSRRAC measurement, a reading at two

nominal supply voltages (3.3 and 5 V) is taken. A second reading is obtained with the same

input signal levels when an ac (200 mVRMS/100 Hz) signal is introduced onto the supply

voltages. Any error introduced by this ac signal is expressed as a percentage of reading.

For the PSRRDC measurement, a reading at two nominal supply voltages (3.3 and 5 V) is

taken. A second reading is obtained with the same input signal levels when the supplies are

varied ±10%. Any error introduced is again expressed as a percentage of the reading.

5.5

Conventions

The lowest analog and digital power supply voltage is named VSS which represents the

system Ground (GND). All voltage specifications for digital input/output pins are referred to

GND.

Positive currents flow into a pin. Sinking current means that the current is flowing into the pin

and is positive. Sourcing current means that the current is flowing out of the pin and is

negative.

The timing specifications of the signal treated by digital control are relative to CLKOUT. This

signal is provided by from the crystal oscillator of 4.194MHz nominal frequency or by the

internal RC oscillator. An external source of 4.194MHz or 8.192MHz can be used.

The timing specifications of signals of the CFGI interface are relative to the SCL-NLC, there

is no direct relationship between the clock (SCL-NLC) of the CFGI interface and the clock of

the DSP block.

A positive logic convention is used in all equations.

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