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AM261...ZNC Datasheet(PDF) 6 Page - Texas Instruments |
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AM261...ZNC Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 218 page  3.1 Functional Block Diagram AM261x Functional Block Diagram is the functional block diagram for this device. 1.5 MB SRAM with ECC AM261x Industrial Connectivity Realtime Cores 2x PRU-ICSS Arm® Cortex®-R5F Arm® Cortex®-R5F Memory Subsystem System Services Power Manager System Monitor DMA Debug Firewall IPC Secure Boot DCC ECC ESM Timers TMU TMU Flash Subsystem (A) OSPI1 UART ECAP MDIO IEP 256KB TCM per core with 32-bit ECC 256KB TCM per core with 32-bit ECC (B) (B) Cores Memory Peripherals PRU0 PRU1 Security HSM (Secure Boot) PKE Debug MD5 3DES AES TRNG SHA Sensing and Actuation 9x Analog Comparators (CMPSS) with DAC Ref 3-port Gb Ethernet Switch (CPSW) w/ IEEE1588 Connectivity RSA USB2.0 4x SPI 6x UART GPIO 3x I2C 3x LIN 2x MCAN 4-bit MMC/SD 8x ECAP 10x EPWM 12-bit DAC 2x 4-ch SDFM 3x EQEP 3x 7-ch ADC FSI GPMC with ELM OSPI0 w/ OptiFlash Figure 3-1. AM261x Functional Block Diagram A. AM261x is available with two and one core options. Refer to the Package Comparison table for more peripheral specific details. B. The R5F cluster supports 512KB of Tightly-Coupled Memory (TCM). When configured as Lockstep operating mode, individual cores can utilize all 512KB. While in Dual-Core mode, each core may only utilize its designated half (256KB TCM). AM2612, AM2611, AM2611-Q1, AM2612-Q1 SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025 www.ti.com 6 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: AM2612 AM2611 AM2611-Q1 AM2612-Q1 |
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