11/18

M35080

POWER ON STATE

After power-on, the memory device is in the follow-

ing state:

– low power stand-by state

– deselected (after power-on, a high-to-low transi-

tion is required on the S input before any opera-

tions can be started).

– the WEL bit is reset

– the SRWD, BP1 and BP0 bits of the status reg-

ister are unchanged from the previous power-

down (they are non-volatile bits).

INITIAL DELIVERY STATE

The device is delivered with the memory array in a

fully erased state. With the exception of the first 32

bytes, all data bits are set to ‘1’, and hence all data

bytes are at FFh. The first 32 bytes are set to all

‘0’s, and hence the first 16 words at 0000h.

The status register bits are initialized to ‘0’, except

for bit b4, which is set to ‘1’, as shown in Table 8.

Figure 12. Page Write Operation Sequence

Note: 1. The most significant address bits, A15-A10, are treated as Don’t Care.

2. The number of clock pulses must be a multiple of 8. Otherwise, the write is aborted.

C

D

AI01796

S

34

33

35 36 37 38 39 40 41 42

44 45 46 47

32

C

D

S

15

2

1

3456789 10

20 21 22 23 24 25 26 27

14 13

3210

28 29 30

INSTRUCTION

16 BIT ADDRESS

0

765432

0

1

DATA BYTE 1

31

43

765432

0

1

DATA BYTE 2

765432

0

1

DATA BYTE 3

65432

0

1

DATA BYTE N

Table 8. Initial Status Register Format

b7

b0

0

0

0

1

000

0