PL133-47SI-R datasheet(8/17 Pages) MICROCHIP

8 / 17 page

PL133-47

DS20007034A-page 8



2026 Microchip Technology Inc. and its subsidiaries

6.0

LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a

performance optimized PCB design:

6.1

Signal Integrity and Termination

Considerations

- Keep traces short

- Trace = Inductor. With a capacitive load this

equals ringing

- Long trace = Transmission Line. Without

proper termination this will cause reflections

ringing and waveforms and degradations.

- Use stripline or microstrip with defined

impedance for long traces (> 1 inch)

- Match traces on one side of the board to

avoid reflections bouncing back and forth.

6.2

Decoupling and Power Supply

Considerations

- Place decoupling capacitors as close as pos-

sible to the VDD pin(s) to limit noise from the

power supply

- Addition of a ferrite bead in series with VDD

can help prevent noise from other board

sources

- Value of decoupling capacitor is frequency

dependent. Typical values to use are 0.1 µF

for designs using frequencies <50 MHz and

0.01 µF for designs using frequencies

>50 MHz

FIGURE 6-1:

Typical CMOS Termination.

Place Series Resistor as close as possible to CMOS output

CMOS Output Buffer

( Typical buffer impedance 20 ohm)

To CMOS Input

50 ohm line

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