TPS73233DBVR datasheet(21/47 Pages) TI2

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7.2.1 Design Requirements

R1 and R2 are calculated for any output voltage using the formula in Figure 7-2. Sample resistor values for

common output voltages are given in Figure 6-2.

For best accuracy, make the parallel combination of R1 and R2 approximately equal to 19kΩ. This 19kΩ, in

addition to the internal 8kΩ resistor, presents the same impedance to the error amplifier as the 27kΩ band-gap

reference output. This impedance helps compensate for leakages into the error amplifier terminals.

7.2.2 Detailed Design Procedure

7.2.2.1 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1μF to 1μF,

low ESR capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources

and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor is necessary if

large, fast rise-time load transients are anticipated or the device is located several inches from the power source.

The TPS732 does not require an output capacitor for stability and has maximum phase margin with no capacitor.

The device is designed to be stable for all available types and values of capacitors. In applications where

multiple low ESR capacitors are in parallel, ringing potentially occurs when the product of COUT and total ESR

drops below 50nF × Ω. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket,

and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance meets this

requirement.

7.2.2.2 Transient Response

The low open-loop output impedance provided by the NMOS pass transistor in a voltage follower configuration

allows operation without an output capacitor for many applications. As with any regulator, the addition of a

capacitor (nominal value 1μF) from the OUT pin to ground reduces undershoot magnitude but increases the

duration. In the adjustable version, the addition of a capacitor, CFB, from the OUT pin to the FB pin also improves

transient response.

The TPS732 does not have active pulldown when the output is overvoltage. This feature allows applications

that connect higher voltage sources, such as alternate power supplies, to the output. This feature also results in

an output overshoot of several percent if the load current quickly drops to zero when a capacitor is connected

to the output. The duration of overshoot is reduced by adding a load resistor. The overshoot decays at a rate

determined by output capacitor COUT and the internal or external load resistance. The rate of decay is given by:

(Fixed voltage versions)

OUT

LOAD

dV / dt

80k

W P

(4)

(Adjustable voltage version)

OUT

LOAD

dV / dt

80k

R ) R

(5)

www.ti.com

TPS732

SBVS037R – AUGUST 2003 – REVISED MAY 2025

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