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TLV9041UIDBVR Datasheet(PDF) 46 Page - Texas Instruments |
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TLV9041UIDBVR Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 78 page  www.ti.com PACKAGE OUTLINE C TYP 6.2 5.8 1.75 MAX 12X 1.27 14X 0.51 0.31 2X 7.62 TYP 0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max height D0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14 0.25 C A B 8 7 PIN 1 ID AREA SEATING PLANE 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800 |
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