6 Detailed Description

6.1 Overview

The ’HC393 devices contain eight flip-flops and additional gating to implement two individual 4-bit counters in a

single package. These devices comprise two independent 4-bit binary counters, each having a clear (CLR) and

a clock (CLK) input. N-bit binary counters can be implemented with each package, providing the capability of

divide by 256. The ’HC393 devices have parallel outputs from each counter stage so that any submultiple of the

input count frequency is available for system timing signals.

6.2 Functional Block Diagram

Figure 6-1. Logic Diagram, Each Counter (Positive Logic)

SN54HC393, SN74HC393

SCLS143E – DECEMBER 1982 – REVISED DECEMBER 2024

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